2. Construct the implementation of 1 to 8 demultiplexer's with its truth table
A 1 to 8 demultiplexer can be implemented using logic gates such as AND gates and NOT gates.
Here is the truth table for a 1 to 8 demultiplexer:
| Control Inputs (S2, S1, S0) | Data Input (D) | Output 0 (Y0) | Output 1 (Y1) | Output 2 (Y2) | Output 3 (Y3) | Output 4 (Y4) | Output 5 (Y5) | Output 6 (Y6) | Output 7 (Y7) |
|-----------------------------|----------------|--------------|--------------|--------------|--------------|--------------|--------------|--------------|--------------|
| 0 0 0 | D | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 0 1 | D | 0 | 0 | 0 | 0 | 0 | 0 | 0 | D |
| 0 1 0 | D | 0 | 0 | 0 | 0 | 0 | 0 | D | 0 |
| 0 1 1 | D | 0 | 0 | 0 | 0 | 0 | D | 0 | 0 |
| 1 0 0 | D | 0 | 0 | 0 | 0 | D | 0 | 0 | 0 |
| 1 0 1 | D | 0 | 0 | 0 | D | 0 | 0 | 0 | 0 |
| 1 1 0 | D | 0 | 0 | D | 0 | 0 | 0 | 0 | 0 |
| 1 1 1 | D | 0 | D | 0 | 0 | 0 | 0 | 0 | 0 |
The implementation of the 1 to 8 demultiplexer can be done using a combination of AND gates and NOT gates according to the truth table. Let's represent the control inputs as S2, S1, and S0 and the data input as D. The outputs Y0 to Y7 can be obtained using the following logic gates:
1. Y0 = D * (S2' * S1' * S0')
2. Y1 = D * (S2' * S1' * S0)
3. Y2 = D * (S2' * S1 * S0')
4. Y3 = D * (S2' * S1 * S0)
5. Y4 = D * (S2 * S1' * S0')
6. Y5 = D * (S2 * S1' * S0)
7. Y6 = D * (S2 * S1 * S0')
8. Y7 = D * (S2 * S1 * S0)
This logic gate combinations represent the implementation of a 1 to 8 demultiplexer.