Determine the values of timer TIM7 prescaler (PSC) and autoreload (ARR) registers so set timer overflow period to 100 ms, if timer clock frequency is 80 MHz:
To determine the values of the timer TIM7 prescaler (PSC) and autoreload (ARR) registers, we need to calculate the number of timer clock cycles required to achieve a timer overflow period of 100 ms.
First, we need to calculate the frequency of the timer clock. The timer clock is derived from the system clock, which in this case is 80 MHz.
Timer clock frequency = System clock frequency / PSC
We want the timer overflow period to be 100 ms, so:
Timer overflow period = (ARR + 1) / Timer clock frequency
Rearranging the equation, we get:
ARR = (Timer overflow period * Timer clock frequency) - 1
Substituting the values, we get:
ARR = (0.1 * 80,000,000) - 1
ARR = 8,000,000 - 1
ARR = 7,999,999
Now we need to select a suitable prescaler value. The prescaler value determines the ratio between the timer clock frequency and the desired timer clock frequency.
PSC = (System clock frequency / Timer clock frequency) - 1
PSC = (80,000,000 / 80,000) - 1
PSC = 1,000 - 1
PSC = 999
To achieve a timer overflow period of 100 ms with a timer clock frequency of 80 MHz, the values of the timer TIM7 prescaler (PSC) and autoreload (ARR) registers should be PSC = 999 and ARR = 7,999,999.
are you sure this answer is correct?
I apologize for the confusion in my previous response. Let's recalculate the values correctly.
To determine the values of the PSC and ARR registers, we can follow these steps:
1. Calculate the timer clock frequency by dividing the system clock frequency by the PSC value:
Timer clock frequency = System clock frequency / (PSC + 1)
Timer clock frequency = 80,000,000 / (PSC + 1)
2. Calculate the timer period in seconds by multiplying the desired overflow period by 0.001 (to convert it to seconds):
Timer period = 0.1 seconds * 0.001 = 0.0001 seconds
3. Calculate the ARR value by subtracting 1 from the timer period divided by the timer clock period:
ARR = (Timer period / (1 / Timer clock frequency)) - 1
ARR = (0.0001 / (1 / (80,000,000 / (PSC + 1)))) - 1
To simplify the calculations, let's select an appropriate PSC value. Since ARR is limited to a 16-bit value, we need to find a PSC value that results in an ARR value within this range.
Let's try a PSC value of 799, which gives us a timer clock frequency of 100,100 Hz.
ARR = (0.0001 / (1 / (80,000,000 / 800))) - 1
ARR = (0.0001 / (1 / 100,000)) - 1
ARR = 10 - 1
ARR = 9
Therefore, to set the timer overflow period to 100 ms with a timer clock frequency of 80 MHz, the values of the TIM7 PSC and ARR registers should be PSC = 799 and ARR = 9.
are you sure?
Apologies for the mistake in my previous response. Let's recalculate the values correctly.
To determine the values of the PSC and ARR registers, we can follow these steps:
1. Calculate the timer clock frequency by dividing the system clock frequency by the PSC value:
Timer clock frequency = System clock frequency / (PSC + 1)
Timer clock frequency = 80,000,000 / (PSC + 1)
2. Calculate the timer period in seconds by multiplying the desired overflow period by 0.001 (to convert it to seconds):
Timer period = 0.1 seconds * 0.001 = 0.0001 seconds
3. Calculate the ARR value by subtracting 1 from the timer period divided by the timer clock period:
ARR = (Timer period / (1 / Timer clock frequency)) - 1
ARR = (0.0001 / (1 / (80,000,000 / (PSC + 1)))) - 1
To simplify the calculations, let's select an appropriate PSC value. Since ARR is limited to a 16-bit value, we need to find a PSC value that results in an ARR value within this range.
Let's try a PSC value of 7999, which gives us a timer clock frequency of 10,001 Hz.
ARR = (0.0001 / (1 / (80,000,000 / 8000))) - 1
ARR = (0.0001 / (1 / 10,000)) - 1
ARR = 1 - 1
ARR = 0
Therefore, to set the timer overflow period to 100 ms with a timer clock frequency of 80 MHz, the values of the TIM7 PSC and ARR registers should be PSC = 7999 and ARR = 0.