Two flip-flops are connected as shown below. The delay represents wiring delay between the two clock inputs, which results in clock skew. This can cause possible loss of synchronization. The flip-flop propagation delay from clock to Q is 10 ns < tp < 15 ns, the set-up and hold times for D1 are always satisfied.
(a) What is the maximum value that the delay can have and still achieve proper synchronous operation? Draw a timing diagram to justify your answer.
(b) Assuming that the delay is < 3 ns, what is the minimum allowable clock period?
To find the maximum value for the delay, we need to consider the worst-case scenario where the delay is the largest. Let's assume the delay is at its maximum value, tp = 15 ns.
(a) Maximum delay required for proper synchronous operation:
In this scenario, we need to analyze the timing relationships between the clock inputs and output of the flip-flops.
- Clock Skew: Clock skew refers to the difference in arrival times of the clock signal at different parts of a circuit. In this case, the clock skew is represented by the delay (15 ns) between the two clock inputs.
- Setup and Hold Times: The setup time (tsu) is the minimum time before the clock edge when the D input should be stable for reliable operation. The hold time (thold) is the minimum time after the clock edge when the D input should remain stable.
Let's assume that for proper synchronous operation, the Q output of the first flip-flop should be stable for at least one clock cycle before it is used as input to the second flip-flop.
Considering the maximum delay (tp = 15 ns), the first flip-flop will have its output stable after 15 ns from the clock edge. This output will then reach the second flip-flop after the delay, resulting in a total delay of 30 ns (15 ns for the first flip-flop and 15 ns for the second flip-flop).
Timing Diagram:
The timing diagram will illustrate the relationship between the clock inputs, the outputs of the flip-flops, and the required stable time for reliable operation.
```
Clock 1 ____________----
| | |
| | |
_______ |
CLK1 | | | _________
_| | | |
D1 _______| |_______| |
| __|______ |____|
| | |
| | | Delay (15 ns)
| | |
__|_|__________|
_________
CLK2 | | |
__________ | | |
| | | | |
| | | | |
| |____| | |
| Flip- _______| |
| Flop 1 | |
|_________| _________ |
| |
| |
| |
__|_______|
CLK3 |
___________|
| |
|___________|
One
Clock Cycle
```
From the timing diagram, we can see that the input to the second flip-flop is stable after one clock cycle (30 ns), which satisfies the setup and hold time requirements.
Therefore, the maximum allowable delay is 15 ns.
(b) Minimum allowable clock period assuming the delay is < 3 ns:
To find the minimum allowable clock period, we need to consider the maximum delay value of 3 ns.
Considering the maximum delay (tp = 3 ns), the total delay between the clock inputs of the flip-flops will be 6 ns (3 ns for the first flip-flop and 3 ns for the second flip-flop).
To achieve proper synchronous operation, the input to the second flip-flop should be stable for at least one clock cycle. Therefore, the minimum allowable clock period can be calculated as follows:
Minimum Allowable Clock Period = 2 * Total Delay
= 2 * 6 ns
= 12 ns
Therefore, the minimum allowable clock period is 12 ns when the delay is less than 3 ns.