engineering (logic systems design)

Two flip-flops are connected as shown below. The delay represents wiring delay between the two clock inputs, which results in clock skew. This can cause possible loss of synchronization. The flip-flop propagation delay from clock to Q is 10 ns < tp < 15 ns, the set-up and hold times for D1 are always satisfied.
(a) What is the maximum value that the delay can have and still achieve proper synchronous operation? Draw a timing diagram to justify your answer.
(b) Assuming that the delay is < 3 ns, what is the minimum allowable clock period?

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asked by Mohamed

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