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Question: 4.7 Problems in this exercise assume that the logic blocks used to implement a processor’s data...
4.7 Problems in this exercise assume that the logic blocks used to implement a processor’s datapath have the following latencies:
1-Mem/D-Mem
Register File
MUX
ALU
Adder
Single gate
Register Read
Register Setup
Sign extend
Control
250 ps
150 ps
25 ps
200 ps
150 ps
5 ps
30 ps
20 ps
50 ps
50 ps
“Register read” is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. “Register setup” is the amount of time a register’s data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File.
4.7.1 [20] Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in Figure 2.20. Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR.
4.7.2 [5] What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)?
4.7.3 [10] What is the latency of LDUR? (Check your answer carefully. Many students place extra muxes on the critical path.)
4.7.4 [10] What is the latency of STUR? (Check your answer carefully. Many students place extra muxes on the critical path.)
4.7.5 [5] What is the latency of CBZ?
4.7.6 [5] What is the latency of B?
4.7.7 [5] What is the latency of an I-type instruction?
4.7.8 [5] What is the minimum clock period for this CPU?
To answer the questions about the latencies and clock period for the CPU in this exercise, we need to refer to the given information about the latencies of various logic blocks used to implement the processor's datapath.
4.7.1: The value of the Reg2Loc control wire can be directly extracted from the instruction because it is available at the same time as the instruction. This is possible because certain opcodes shown in Figure 2.20 allow us to extract this value directly from the instruction. The R-type instructions (except for LSR and LSL which do not use the Rm field) have the necessary opcode information to determine the value of Reg2Loc. We can therefore use this information to extract the value of Reg2Loc directly from the instruction.
4.7.2: The latency of an R-type instruction is the time it takes for the instruction to complete its execution. In this case, we need to consider the latencies of the logic blocks involved in the execution of an R-type instruction. According to the given information, the latencies for the required logic blocks are as follows:
- Register Read: 30 ps
- Register Setup: 20 ps
- ALU: 200 ps
To ensure that the R-type instruction works correctly, the clock period should be equal to or greater than the sum of these latencies. Therefore, the latency of an R-type instruction is 30 ps + 20 ps + 200 ps = 250 ps.
4.7.3: The latency of LDUR instruction is the time it takes for the instruction to complete its execution. To determine this, we need to consider the latencies of the logic blocks involved in the execution of the LDUR instruction. According to the given information, the latencies for the required logic blocks are as follows:
- Register Read: 30 ps
- Register Setup: 20 ps
- MUX: 25 ps
- Mem/D-Mem: 250 ps
To check our answer carefully and avoid placing extra muxes on the critical path, we should consider the longest path among these latencies. Therefore, the latency of LDUR instruction is 30 ps + 20 ps + 250 ps = 300 ps.
4.7.4: The latency of STUR instruction is the time it takes for the instruction to complete its execution. To determine this, we need to consider the latencies of the logic blocks involved in the execution of the STUR instruction. According to the given information, the latencies for the required logic blocks are as follows:
- Register Read: 30 ps
- Register Setup: 20 ps
- MUX: 25 ps
- Mem/D-Mem: 250 ps
To check our answer carefully and avoid placing extra muxes on the critical path, we should consider the longest path among these latencies. Therefore, the latency of STUR instruction is 30 ps + 20 ps + 250 ps = 300 ps.
4.7.5: The latency of CBZ instruction is the time it takes for the instruction to complete its execution. However, the given information does not provide specific latencies for the logic blocks involved in the execution of the CBZ instruction. Therefore, we cannot determine the exact latency of CBZ instruction based on the given information.
4.7.6: The latency of B instruction is the time it takes for the instruction to complete its execution. However, the given information does not provide specific latencies for the logic blocks involved in the execution of the B instruction. Therefore, we cannot determine the exact latency of B instruction based on the given information.
4.7.7: The latency of an I-type instruction is the time it takes for the instruction to complete its execution. However, the given information does not provide specific latencies for the logic blocks involved in the execution of an I-type instruction. Therefore, we cannot determine the exact latency of an I-type instruction based on the given information.
4.7.8: The minimum clock period for this CPU should be equal to or greater than the sum of the latencies of all the logic blocks involved in the execution of the longest instruction. In this case, we can consider the LDUR instruction, which has the longest path among the given instructions. According to the given information, the latencies for the required logic blocks in LDUR instruction are as follows:
- Register Read: 30 ps
- Register Setup: 20 ps
- MUX: 25 ps
- Mem/D-Mem: 250 ps
Therefore, the minimum clock period for this CPU should be 30 ps + 20 ps + 25 ps + 250 ps = 325 ps.
To find the answers to the given questions, we need to analyze the provided information about the latencies of the logic blocks used in the processor's datapath. Let's break down each question and explain how to find the answers.
4.7.1 [20] - To extract the value of the Reg2Loc control wire directly from the instruction, we need to examine the opcodes shown in Figure 2.20. By carefully examining the opcodes, we can determine if the instruction is an LSR or LSL type, as they do not use the Rm field. Finally, we can ignore STXR. The correct value of Reg2Loc control wire is available at the same time as the instruction.
4.7.2 [5] - The latency of an R-type instruction refers to how long the clock period should be to ensure that this instruction works correctly. To find the latency, we need to consider the slowest logic block in the datapath, which is the Register File with a latency of 150 ps. Therefore, the clock period should be at least 150 ps to ensure correct operation.
4.7.3 [10] - The latency of LDUR refers to how long it takes for an LDUR instruction to execute. To find the latency, we need to identify the critical path, i.e., the path with the longest latency. It is important to check for any extra muxes placed on the critical path, as they might introduce additional delay. By carefully examining the datapath, we can identify the critical path and determine the LDUR's latency.
4.7.4 [10] - Similar to question 4.7.3, the latency of STUR refers to the time it takes for an STUR instruction to execute. We need to identify the critical path and check for any extra muxes on it to find the correct latency of STUR.
4.7.5 [5] - The latency of CBZ refers to the time it takes for a CBZ instruction to execute. To find the latency, we need to identify the critical path and determine the delay introduced by the logic blocks on that path.
4.7.6 [5] - The latency of B refers to the time it takes for a B instruction to execute. Similar to previous questions, we need to identify the critical path and calculate the delay introduced by the logic blocks on that path.
4.7.7 [5] - The latency of an I-type instruction refers to the time it takes for an I-type instruction to execute. Again, we need to identify the critical path and calculate the delay introduced by the logic blocks on that path.
4.7.8 [5] - The minimum clock period for this CPU refers to the shortest time duration between clock cycles that allows correct operation. To find this period, we need to consider the longest latency of any logic block in the datapath and set the clock period to be at least that long.
By carefully analyzing the information provided about the latencies and following the instructions stated for each question, we can find the correct answers.