Wednesday
April 16, 2014

Homework Help: computer sciece

Posted by Tracy on Sunday, November 27, 2011 at 11:15am.

Baud Rate Generator:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity br_gen is
generic(divisor: integer := 3);
port(
sysclk:in std_logic; --system clock
sel :in std_logic_vector(2 downto 0);
bclkx4:buffer std_logic; --baud rate X 8
bclk :out std_logic --baud rate
);
end br_gen;
architecture arch of br_gen is
signal cnt2,clkdiv: std_logic;
signal ctr1: std_logic_vector (3 downto 0):= "0000";--changed from 7 to 3
signal ctr2: std_logic_vector (2 downto 0):= "000"; --changed from 2 to 1 and 000 to 00
begin
----- clk divider -----
process (sysclk)
variable cnt1 : integer range 0 to divisor;
variable divisor2 : integer range 0 to divisor;
begin
divisor2 := divisor/2;
if (sysclk'event and sysclk='1') then
if cnt1=divisor then
cnt1 := 1;
else
cnt1 := cnt1 + 1;
end if;
end if;
if (sysclk'event and sysclk='1') then
if (( cnt1=divisor2) or (cnt1=divisor)) then
cnt2 <= not cnt2;
end if;
end if;
end process;
clkdiv<= cnt2 ;
----- 8 bits counter -----
process (clkdiv)
begin
if(rising_edge(clkdiv)) then
ctr1 <= ctr1+1;
end if;
end process;
----- MUX -----
bclkx4<=ctr1(CONV_INTEGER(sel));
----- clkdiv8 -----
process (bclkx4)
begin
if(rising_edge(bclkx4)) then
ctr2 <= ctr2+1;
end if;
end process;
bclk <= ctr2(1);
end arch;

--------------------------------------
-------------------------------------------------------------------
Receiver:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity receiver is
port(
sysclk :in std_logic;
rst_n :in std_logic;
bclkx4 :in std_logic;
rxd :in std_logic;
rxd_readyH:out std_logic;
RDR:out std_logic_vector(3 downto 0)
);
end receiver;

architecture arch of receiver is
type statetype is (idle,start_detected,recv_data);
signal state,nextstate:statetype;
signal inc1,inc2,clr1,clr2:std_logic;
signal shftRSR,load_RDR:std_logic;
signal bclkx4_dlayed,bclkx4_rising:std_logic;
signal RSR:std_logic_vector(3 downto 0);
signal ct1:integer range 0 to 7;
signal ct2:integer range 0 to 8;
signal ok_en: std_logic;
begin
bclkx4_rising<=bclkx4 and(not bclkx4_dlayed);
---------- FSM of UART receiver ---------
process(state,rxd,ct1,ct2,bclkx4_rising)
begin
----- initial value -----
inc1<='0';inc2<='0';clr1<='0';clr2<='0';
shftRSR<='0';load_RDR<='0';ok_en<='0';
----- state machine -----
case state is
----- idle state; standby, wait until rxd='0' -----
when idle=>
if (rxd='0') then
nextstate<=start_detected;
else
nextstate<=idle;
end if;
----- start_detected state; determine whether start bit -----
when start_detected=>
if (bclkx4_rising='0') then
nextstate<=start_detected;
elsif (rxd='1') then
clr1<='1';
nextstate<=idle;
elsif (ct1=3) then
clr1<='1';
nextstate<=recv_data;
else
inc1<='1';
nextstate<=start_detected;
end if;
----- receive data state ----
when recv_data=>
if (bclkx4_rising='0') then
nextstate<=recv_data;
else
inc1<='1';
if (ct1/=3) then
nextstate<=recv_data;
elsif (ct2/=4) then
shftRSR<='1';
inc2<='1';
clr1<='1';
nextstate<=recv_data;
elsif (rxd='0') then
nextstate<=idle;
clr1<='1';
clr2<='1';
else
load_RDR<='1';
ok_en<='1';
clr1<='1';
clr2<='1';
nextstate<=idle;
end if;
end if;
end case;
end process;
---------- update state and value of register ----------
process(sysclk,rst_n)
begin
if (rst_n='0') then
state<=idle;
bclkx4_dlayed<='0';
ct1<=0;
ct2<=0;
RDR<="0000";
elsif (sysclk'event and sysclk='1') then
state<=nextstate;
if(clr1='1')then ct1<=0;elsif(inc1='1')then ct1<=ct1+1;end if;
if(clr2='1')then ct2<=0;elsif(inc2='1')then ct2<=ct2+1;end if;
if(shftRSR='1')then RSR<=rxd & RSR(3 downto 1);end if;
if(load_RDR='1')then RDR<=RSR;end if;
if(ok_en='1')then rxd_readyH<='1';else rxd_readyH<='0';end if;
---- generator bclk delay signal for determine bclkx4 rising ----
bclkx4_dlayed<=bclkx4;
end if;
end process;
end arch;


-------------------------------------------------------------------
---------------------------------------------
Transmitter:
library ieee;
use ieee.std_logic_1164.all;
entity transmitter is
port(
sysclk : in std_logic;
rst_n : in std_logic;
bclk : in std_logic;
txd_startH : in std_logic;
DBUS : in std_logic_vector(3 downto 0);
txd_doneH : out std_logic;
txd : out std_logic
);
end transmitter;
architecture arch of transmitter is
type statetype is (idle, synch, tdata);
signal state, nextstate : statetype;
signal tsr:std_logic_vector (4 downto 0);
signal bct: integer range 0 to 9;
signal inc, clr, loadTSR, shftTSR, start: std_logic;
signal bclk_rising, bclk_dlayed, txd_done: std_logic;
begin
txd <= tsr(0);
txd_doneH <= txd_done;
bclk_rising <= bclk and (not bclk_dlayed);
process(state, txd_startH, bct, bclk_rising)
begin
inc <= '0';
clr <= '0';
loadTSR <= '0';
shftTSR <= '0';
start <= '0';
txd_done <= '0';
case state is
----- idle state; wait until txd_startH = '1' -----
when idle =>
if (txd_startH = '1' ) then
loadTSR <= '1';
nextstate <= synch;
else
nextstate <= idle;
end if;
----- synch state -----
when synch =>
if (bclk_rising = '1') then
start <= '1';
nextstate <= tdata;
else
nextstate <= synch;
end if;
----- transmit data state -----
when tdata =>
if (bclk_rising = '0') then
nextstate <= tdata;
elsif (bct /= 9) then
shfttsr <= '1';
inc <= '1';
nextstate <= tdata;
else
clr <= '1';
txd_done <= '1';
nextstate <= idle;
end if;
end case;
end process;
----- update data -----
process (sysclk, rst_n)
begin
if (rst_n = '0') then
tsr <= "11111";
state <= idle;
bct <= 0;
bclk_dlayed <= '0';
elsif (sysclk'event and sysclk = '1') then
state <= nextstate;
--counter of transmit bit
if (clr = '1') then
bct <= 0;
elsif (inc = '1') then
bct <= bct + 1;
end if;
--TSR assignment
if (loadtsr = '1') then
TSR <= DBUS & '1';
elsif (start = '1') then
TSR(0) <= '0';
elsif (shftTSR = '1') then
TSR <= '1' & TSR( 4 downto 1);
end if;
-- Bclk delayed by 1 sysclk
bclk_dlayed <= bclk;
end if;
end process;
end arch;
-------------------
-------------------
Can someone tell me the Usage of this code......

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